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Category Title Patent Number Issue Date Assignee ↑  
Other Method and system for recoding noneffective instructions within a data processing system US5619408 04-08-1997 IBM
Other Method for interfacing applications with a content addressable memory US5615360 03-25-1997 IBM
Other Decreasing processing time for type 1 dyadic instructions US5253349 10-12-1993 IBM
Other Message queue processing among cooperative processors having significant speed differences US5224215 06-29-1993 IBM
Interfacing System and method for handling storage consistency conflict US6237067 05-22-2001 IBM
Interfacing High performance multichannel DMA controller for a PCI host bridge with a built-in cache US6230219 05-08-2001 IBM
Interfacing Read request performance of a multiple set buffer pool bus bridge US6219737 04-17-2001 IBM
Interfacing Alternating data valid control signals for high performance data transfer US5671370 09-23-1997 IBM
Interfacing Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required US5659696 08-19-1997 IBM
Interfacing Independent computer storage addressing in input/output transfers US5634007 05-27-1997 IBM

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