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Patent Title: Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode

Assignee: IBM
Patent Number: US6178467
Issue Date: 01-23-2001
Application Number:
File Date:07-07-1998

Abstract: A method and system for transferring data between a processor and a device residing at a non-cacheable address. The method includes the steps of asserting the non-cacheable address onto an address bus, asserting a first signal indicating that the processor has data ready for burst mode transfer between the processor and a device residing at the non-cacheable address, asserting a second signal indicating that the device is ready for the burst mode transfer, and performing a burst mode transfer of a plurality of bytes between the processor and the non-cacheable address. The method of the invention provides both sequential and non-sequential burst transfer modes. The system of the invention provides a processor, a device, bus control logic, and non-cacheable address logic. The bus control logic and the non-cacheable address logic are configured to implement new semantic meanings for the CACHE# and KEN# signals that eliminate the distinction between cacheable and non-cacheable address space for purposes of allowing burst mode transfers.

Notes:

Link to USPTO

IBM Pledge dated 1/11/2005