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Patent Title: Apparatus and method for modeling parallel processing of instructions using sequential execution hardware

Assignee: IBM
Patent Number: US5179672
Issue Date: 01-12-1993
Application Number:
File Date:06-19-1990

Abstract: A system for modeling computer instruction execution is disclosed. The public status register holds data representative of the status of the computer processing system. A combinational logic unit receives multibit data words from the public status register, as well as a source of program code. The combinational logic unit produces output data implementing a computer processor. A working status register, connected to the combinational logic unit, receives the combinational logic unit output signals. A clock signal generator, during first and second clock intervals, transfers the data from the working status register to the public status register only after all the combinational logic units have provided their output data for a given set of input data. A second clock interval will clock the public status register contents to the input of the combinational logic unit when a subsequent set of program code is presented to the combinational logic unit.


Link to USPTO

IBM Pledge dated 1/11/2005