Patent Title: System and method for allocating bus resources in a data processing system
Abstract: An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master processor. The system controller issues an address bus grant, in response to an address bus request from a particular bus device, and shortly after that issues another signal notifying the granted bus device that it must now disable the address bus. Furthermore, upon receipt of the signal indicating disablement of the address bus, other bus devices may then snoop, or sample, the address bus.