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Patent Title: Lifetime-sensitive instruction scheduling mechanism and method

Assignee: IBM
Patent Number: US6305014
Issue Date: 10-16-2001
Application Number:
File Date:06-18-1998

Abstract: An instruction scheduler in an optimizing compiler schedules instructions in a computer program by determining the lifetimes of fixed registers in the computer program. By determining the lifetimes of fixed registers, the instruction scheduler can achieve a schedule that has a higher degree of parallelism by relaxing dependences between instructions in independent lifetimes of a fixed register so that instructions can be scheduled earlier than would otherwise be possible if those dependences were precisely honored.


Link to USPTO

IBM Pledge dated 1/11/2005