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Patent Title: Method and apparatus to maintain cache coherency in a multiprocessor system with each processor's private cache updating or invalidating its contents based upon set activity

Assignee: IBM
Patent Number: US5228136
Issue Date: 07-13-1993
Application Number:
File Date:01-10-1991

Abstract: A cache coherency mechanism enabling efficient and dynamic switching between the maintenance protocols of the invalidate and update types. The mechanism can reduce traffic on the shared bus and improve the system performance. Usually each processor repeatedly accesses a limited area of the memory within a short span of time. That area is referred to as a "working set" with respect to the processor. Each time a write operation occurs to shared data, each of the sharing processors determines whether or not the data belongs to its working set. If a sharing processor determines that the data belongs to its working set, then the cache consistency is maintained by the update type of procedure. Otherwise cache consistency is maintained via the invalidate type of procedure. In one embodiment the invention improves the system performance by utilizing the above mechanism for determining the working set in conjunction with a new cache protocol, ALL.sub.-- READ. A plurality of processors in a multiprocessor system using snoopy caches frequently share data or instruction code at one address. According to the ALL.sub.-- READ protocol when a processor causes a read miss for data or code at an address, other processors likely to use the data or code automatically read it into their caches. By using the working set determination mechanism, only data in the working set is applied with ALL.sub.-- READ. This invention thereby provides ALL.sub.-- READ efficiently, reduces bus traffic and improves the system performance.


Link to USPTO

IBM Pledge dated 1/11/2005