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Patent Title: Method and system for concurrent access in a data cache array utilizing multiple match line selection paths

Assignee: IBM
Patent Number: US5640534
Issue Date: 06-17-1997
Application Number:
File Date:10-05-1994

Abstract: An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. A separate effective address port and real address port permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port and the real address port. Each access port provides reference lines into either the first content addressable field or the second content addressable field, and a match line associated with each content addressable field is then precharged and discharged in response to a failure of the content of an associated content addressable field to match the desired data. A normal word line is provided and activated by either the effective address match line or the real address match line through the subarray arbitration circuit so that only one match line is allowed to drive the normal word line concurrently. In the event of a SNOOP access, the real address match line may also be utilized to activate a separate SNOOP word line. The separate SNOOP word line and the normal word line are both coupled to dual ported bits within the data status field, permitting concurrent access of those bits during normal load/cache operations which utilize the effective address match line.


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