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Patent Title: Demand-based issuance of cache operations to a system bus

Assignee: IBM
Patent Number: US6182201
Issue Date: 01-30-2001
Application Number:
File Date:04-14-1997

Abstract: A method of managing and speculatively issuing architectural operations in a computer system is disclosed. A first architectural operation at a first coherency granule size is issued and translated into a large-scale architectural operation. The first architectural operation can be a first cache instruction directed to a memory block, and the translating results in a page-level cache instruction being issued which is directed to a page that includes the memory block. The large-scale architectural operation is transmitted to a system bus of the computer system. A system bus history table may be used to store a record of the large-scale architectural operations. The history table then can be used to filter out any later architectural operation that is subsumed by the large-scale architectural operation. The history table monitors the computer system to ensure that the large-scale architectural operations recorded in the table are still valid.


Link to USPTO

IBM Pledge dated 1/11/2005