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Patent Title: Method and apparatus for interrupt load balancing for powerPC processors

Assignee: IBM
Patent Number: US6189065
Issue Date: 02-13-2001
Application Number:
File Date:09-28-1998

Abstract: Interrupts from an I/O subsystem are first directed to a single processor in a multiple superscalar processor data processing system. If an interrupt load on the processor is sufficiently high, the interrupt is sent (offloaded) to a second specific processor. The process continues throughout all superscalar processors in the data processing system and each processor builds interrupt prediction data corresponding to the interrupt load. A threshold counter may be added to the logic so offloading does not take place until a specified number of interrupts are queued within that specific processor, thus providing a fixed level of prediction data. Some processors may be left out of the offload string so they are not disturbed by an interrupt.


Link to USPTO

IBM Pledge dated 1/11/2005