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Patent Title: Pipelined two-cycle branch target address cache

Assignee: IBM
Patent Number: US6279105
Issue Date: 08-21-2001
Application Number:
File Date:10-15-1998

Abstract: In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.


Link to USPTO

IBM Pledge dated 1/11/2005