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Patent Title: Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor

Assignee: IBM
Patent Number: US6298435
Issue Date: 10-02-2001
Application Number:
File Date:04-16-1996

Abstract: A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the physical rename registers may not yet be available. These virtual rename buffers are assigned by a buffer pointer assignment table. A virtual bit implemented along with each of the physical rename registers is flipped when an instruction corresponding to the entry stored within a particular physical rename register is completed and the result written to the architected register. Thus, at dispatch time, rename registers are assigned as if there were more rename buffers than there existed physical rename registers.


Link to USPTO

IBM Pledge dated 1/11/2005