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Patent Title: Optimizing compiler for generating store instructions having memory hierarchy control bits

Assignee: IBM
Patent Number: US6249911
Issue Date: 06-19-2001
Application Number:
File Date:08-05-1999


Abstract: An optimizing compiler for generating STORE instructions having memory hierarchy control bits is disclosed. The compiler first converts a first STORE instruction to a second STORE instruction. The compiler then provides an operation code field within the second instruction for indicating an updating operation. The compiler further provides a vertical write-through level field within the second instruction for indicating a vertical memory level and a horizontal memory level within a multi-level memory hierarchy to which the updating operation should be applied.

Notes:

Link to USPTO

IBM Pledge dated 1/11/2005