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Patent Title: Protocol and system for performing line-fill address during copy-back operation

Assignee: IBM
Patent Number: US5687350
Issue Date: 11-11-1997
Application Number:
File Date:02-10-1995


Abstract: A protocol and system for providing a next read address during an address phase of a write transaction in a data cache unit in a processing unit is disclosed. The processing unit includes the data cache unit and an instruction cache unit both coupled to an address bus and a data bus, respectively. The two buses are further connected to a system memory controller separate from the microprocessor. The protocol and system provide for next read address and a next transaction during the address phase in a current write transaction. The protocol loads a pre-fetched address within a current data transaction and then generates a next line fill address using the pre-fetched address which is concatenated to the current data transaction. The pre-fetched address is used to generate a next line fill address. The line fill address is generated upon determining if a cache read miss has occurred and if so, copying a modified cache line back to the main system memory and then loading the missed cache read line into the internal cache from the system memory controller.

Notes:

Link to USPTO

IBM Pledge dated 1/11/2005