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Patent Title: Cache coherency protocol having hovering (H), recent (R), and tagged (T) states

Assignee: IBM
Patent Number: US6272603
Issue Date: 08-07-2001
Application Number:
File Date:02-17-1998


Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the address tag is valid and that the first data item is invalid. If, while the coherency indicator is set to the first state, the first cache receives a data transfer on the interconnect associated with the address indicated by the address tag, where the data transfer includes a second data item that is modified with respect to a corresponding data item in the system memory, the second data item is stored in the first cache in association with the address tag. In addition, the coherency indicator is updated to a second state indicating that the second data item is valid and that the first cache is responsible for writing back the second data item to system memory.

Notes:

Link to USPTO

IBM Pledge dated 1/11/2005