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Patent Title: Read request performance of a multiple set buffer pool bus bridge

Assignee: IBM
Patent Number: US6219737
Issue Date: 04-17-2001
Application Number:
File Date:12-10-1998

Abstract: A bus bridge coupled between primary and secondary busses including a buffer pool with first and second buffer sets and steering logic configured to direct transactions received from first and second peripheral devices to the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions posted in the first buffer set onto the primary bus ahead of and in response to a read request transaction from the first peripheral device while leaving transactions in the second buffer set unaffected. In one embodiment, the steering logic is configured to receive first and second grant signals produced by arbitration logic of the bridge. The first and second grant signals indicate mastership of the secondary bus and the source of a subsequent transaction to be received via the secondary bus. The bridge and the secondary bus are suitably compliant with the PCI protocol. The primary bus may be the host bus of a processor unit or a peripheral bus such as a PCI bus. The invention further contemplates a computer system including processor, a bus bridge as described coupled to the processor via a primary bus, a system memory, and first and second peripheral devices coupled to the bridge via a secondary bus. The bridge is configured to push posted memory write transactions stored in the first buffer set onto the primary bus ahead of a read request from the first peripheral device without affecting transactions stored in the second buffer set. The bridge is preferably configured to arbitrate mastership of the secondary bus among the peripheral devices in response to first and second request signals received by the bridge from the first and second peripheral devices respectively.

Notes:

Link to USPTO

IBM Pledge dated 1/11/2005